Blog

By Marcos Gouveia (INESC TEC)

 

The EPICURE HPC in ARM Architecture Hackathon took place from 4–7 February 2025 at INESC TEC’s hub, Universidade do Minho, Braga, Portugal. This was the second hackathon organised by the EPICURE Advanced Training Work Package, following the EPICURE GPU Hackathon held in Bologna in October 2024.

 

Over the last decade, there has been an increase in the availability of HPC infrastructures powered by CPUs with ARM architectures—the most notable example being the Fugaku supercomputer, which in June 2020 earned the title of the world’s fastest supercomputer by placing first on the TOP500 list. In the EuroHPC ecosystem, Deucalion is currently the only supercomputer with a dedicated ARM partition that is accessible via EuroHPC calls. It will soon be joined by Jupyter, the first exascale EuroHPC system.

 

With the future of HPC closely tied to developments in ARM architecture, the objective of the EPICURE HPC in ARM Hackathon was to give participants the opportunity to use Deucalion’s ARM partition, not only to test the differences between x86 and ARM systems, but also to prepare their software to run efficiently on this architecture.

 

The first two days of the hackathon were dedicated to lectures delivered by experienced users and developers of ARM software and hardware. The event kicked off with John Wagner (Fujitsu), the “architect” of Deucalion’s ARM partition, who introduced the A64FX processor used in the system. The first day concluded with a visit to the Deucalion machine.

 

The second day focused on topics such as porting code from x86 to ARM, running Artificial Intelligence workflows on Deucalion, and comparing the performance of OpenFOAM across architectures. The day ended with a talk by Kenneth Hoste on running optimised software on the ARM partition using the European Environment for Scientific Software (EESSI).

 

The final two days centred on hands-on sessions, during which participants worked on their projects under the guidance of experienced mentors. Project topics ranged from AI applications and industrial problems to particle physics simulations. This thematic variety enriched the event and demonstrated that the usefulness of ARM processors is recognised across a broad spectrum of the HPC community.

 

Anthoni Alcaraz-Torres, a postdoctoral researcher at the Catalan Institute of Nanoscience and Nanotechnology, attended the hackathon with the goal of testing the electronic structure code SIESTA on ARM CPUs. Mentored by Miguel Dias Costa (University of Coimbra) and Bernardo Malaca (CNCA), Anthoni worked on optimising an EasyBuild recipe for SIESTA. This effort, initiated during the hackathon, continued afterwards and led to a working, optimised EasyBuild recipe successfully integrated into the EESSI software stack. This work was featured in a post by the MAX CoE, accessible at: https://www.max-centre.eu/news/siesta-522-running-arm-deucalion-global-release-through-eessi.

 

João Cartaxo, a master’s student in Physics from the University of Coimbra, working on neutron star physics, described his participation in the hackathon as an “incredibly rewarding experience,” noting the outstanding support from mentors during the hands-on sessions. He praised the event as “a fun and engaging experience that combined technical growth with a great collaborative atmosphere.” Technically, João was able to compare the performance of his original x86 code with the ARM version he developed during the hackathon and was pleased with the preliminary results.

 

In 2025, the EPICURE Training Work Package will organise two more hackathons: one led by the EPICURE team at KTH (Sweden) and another hosted again by INESC TEC (Portugal). Stay tuned!